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dear customers, about the change in the name such as "oki electric industry co. ltd." and "oki" in documents to oki semiconductor co., ltd. the semiconductor business of oki electric industry co., ltd. was succeeded to oki semiconductor co., ltd. on oc tober 1, 2008. therefore, please accept that although the terms and marks of "oki electric indust ry co., ltd.", ?oki electric?, and "oki" remain in the documents, they all have been changed to "oki semiconductor co., ltd.". it is a change of the company name, the co mpany trademark, and the logo, etc. , and not a content change in documents. october 1, 2008 oki semiconductor co., ltd. 550-1 higashiasakawa-cho, hachio ji-shi, tokyo 193-8550, japan http://www.okisemi.com/en/
msm5265 ? semiconductor 1/18 ? semiconductor msm5265 80-dot lcd driver e2b0008-27-y2 general description the msm5265 is an lcd driver which can directly drive up to 80 segments in the static display mode and up to 160 segments in the 1/2 duty dynamic display mode. the msm5265 is fabricated with low power cmos metal gate technology. the msm5265 consists of a 160-stage shift register, 160-bit data latch, 80 pairs of lcd drivers and a common signal generator. the display data is serially input from the data-in pin to the 160-stage shift register synchronized with the clock pulse. the data is shifted into the 160-bit data latch by the load signal. then the latched data is directly output to the lcd from the 80 pairs of lcd drivers as a serial output. the common signal can be generated by the built-in generator, or externally input. the common synchronization circuit which is used in the dynamic display mode is integrated on the chip. features ? supply voltage : 3.0 to 6.0 v ? drives lcd of up to 80 segments (in the static display mode) ? drives lcd of up to 160 segments (in the 1/2 duty dynamic display mode) ? simple interface with microcomputer ? bit-to-bit correspondence between input data and output data h: display on l: display off ? can be cascade-connected ? built-in common signal generator ? can be synchronized with the external common signal ? testing pins for all-on (seg-test) and all-off (blank) ? applicable as an output expander ? lcd driving voltage can be adjusted by the combination of v lc1 and v lc2 ? package options: 100-pin plastic qfp (qfp100-p-1420-0.65-k) (product name : msm5265gs-k) 100-pin plastic qfp (qfp100-p-1420-0.65-bk) (product name : MSM5265GS-BK) this version: nov. 1997 previous version: mar. 1996
msm5265 ? semiconductor 2/18 block diagram 80-dot segment driver 80-ch data selector (a) 80-bit data latch (b) 80-bit data latch (a) 80-stage shift register (b) 80-stage shift register osc 1/4 or 1/8 1/2 common driver sync circuit seg 80 seg 1 to lcd panel 80 80 80 seg-test blank v dd gnd load data-in clock d/s osc-out osc-out osc-in ext/int sync data-out 2 data-out 1 v lc1 v lc2 com-a com-b com-out
msm5265 ? semiconductor 3/18 pin configuration (top view) 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 seg51 seg52 seg53 seg54 seg55 seg56 seg57 seg58 seg59 seg60 seg61 seg62 seg63 seg64 seg65 seg66 seg67 seg68 seg69 seg70 seg71 seg72 seg73 seg74 seg75 seg76 seg77 seg78 seg79 seg80 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 v lc2 com-b com-a v lc1 com-out sync blank seg-test gnd d/s v dd ext/int osc-in osc-out osc-out data-out2 data-out1 data-in clock load 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 seg48 seg49 seg50 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 100-pin plastic qfp
msm5265 ? semiconductor 4/18 absolute maximum ratings recommended operating conditions ? oscillation circuit r 0 r 1 osc-out c 0 osc-out (msm5265) osc-in supply voltage v dd C0.3 to +6.5 v t a = 25c input voltage v i gndC0.3 to v dd +0.3 v t a = 25c storage temperature t stg C55 to +150 c parameter symbol condition rating unit parameter min. oscillator resistance symbol condition typ. max. unit corresponding pin 56 r 0 100 220 k w osc-out oscillator capacitance 0.001 c 0 film capacitor 0.047 m f osc-out current limiting resistance 0.56 r 1 r 1 3 10 r 0 1 2.2 m w osc-in common signal frequency 25 f com 150 hz com-a com-b supply voltage v dd 3 to 6 v operating temperature t op C40 to +85 c lcd driving voltage v lcd 3 to v dd v v dd Cv lc2 parameter symbol condition range unit
msm5265 ? semiconductor 5/18 electrical characteristics dc characteristics parameter symbol condition applicable pin min. typ. max. unit "h" input voltage "l" input voltage input leakage current v ih v il i il v i = 5.0 v/0 v 36 v dd v gnd 1.0 v 1 m a seg-test, blank, load, data-in, clock, d/s, ext/int, osc-in "h" output voltage v oh i o = C100 m a 4.5 v data-out1 data-out2 com-out v lc1 = 2.5 v, v lc2 = 0 v i o = C30 m a 4.8 v osc-out osc-out seg 1 -seg 80 v lc1 = 2.5 v, v lc2 = 0 v i o = C150 m a 4.8 v com-a com-b "m" output voltage v om v lc1 = 2.5 v, v lc2 = 0 v i o = 150 m a 2.3 2.7 v com-a com-b data-out1 data-out2 com-out "l" output voltage v ol i o = 100 m a 0.5 v i o = C200 m a 4.5 v osc-out osc-out i o = 200 m a 0.5 v v lc1 = 2.5 v, v lc2 = 0 v i o = 30 m a 0.2 v seg 1 - seg 80 v lc1 = 2.5 v, v lc2 = 0 v i o = 150 m a 0.2 v com-a com-b i o = 250 m a 0.8 v sync output leakage current segment output impedance i lo v o = 5 v when internal tr is off 5 m a seg 1 - seg 80 r seg v lc1 = (5+v lc2 )/2 v lc2 = 0 to 2 v 10 k w sync (v dd = 5.0 v ta =C40 to +85c)
msm5265 ? semiconductor 6/18 v l v l (v h = 0.8 v dd , v l = 0.2 v dd ) v l v h t phl t plh t f -l v l v h v h t l v h v l v h v l t f h v l t f -d t f l t d- f v h v h v l v l t s data-in clock load data-out 1 data-out 2 sync switching characteristics parameter com-a com-b static supply current dynamic supply current symbol v dd i dd1 i dd2 applicable pin v lc1 = (5+v lc2 )/2 v lc2 = 0 to 2 v fix all input levels at either v dd or gnd no load. r 0 = 100 k w , c 0 = 0.01 m f, r 1 = 1 m w common output impedance condition min. typ. max. unit 1.5 k w 100 m a 0.5 ma 0.12 r com parameter symbol condition min. max. unit applicable pin clock frequency f f 1 mhz clock pulse "h" time f f h 0.3 m s clock clock pulse "l" time f f l 0.5 m s data setup time f dC f 0.1 m s data-in clock data hold time f f Cd 0.1 m s "h"? "l" propagation delay time t phl t plh load capacitance of data-out1, data-out2: 15 pf 0.8 m s data-out1 data-out2 clock load pulse "h" time t l 0.2 m s load clock ? load time t f Cl 0.1 m s clock load osc-in input frequency f osc 5 khz osc-in sync pulse "l" time t s 0.2 m s sync (v dd = 3.0 to 6.0 v ta = C40 to +85c)
msm5265 ? semiconductor 7/18 functional description operational description the msm5265 consists of a 160-stage shift register, 160-bit data latch, and 80 pairs of lcd drivers. the display data is input from the data-in pin to the 160-stage shift register at the rising edge of the clock pulse and it is shifted to the 160-bit data latch when the load signal is set at "h" level, then it is directly output from the 80 pairs of lcd drivers to the lcd panel. input the display data in the order of seg80, seg79, seg78, ..., seg2, seg1. data latch output (inside the ic) 123456159160 data-in clock load pin functional description ? osc-in, osc-out, osc-out as shown in the figure below, by connecting the external resistors r 0 , r 1 and external capacitor c 0 with osc-in, osc-out and osc-out respectively, an oscillating circuit to generate the common signal is formed. this frequency is divided into either 1/8 or 1/4 by the internal dividing circuit. the 1/8 divided frequency is used in the static display mode, while the 1/4 divided frequency is used as the common signal in the 1/2 duty dynamic display mode which is output from the com- out pin. (ext/int should be set at low level.) the resistor r 1 is used to limit the current on the osc-in pin's protecting diodes. the value of the r 1 should be more than 10 times that of r 0 . when the external common signal is used, the ext/int pin should be set at high level and the external common signal should be input from the osc-in pin. keep the wiring between the osc-in pin and r 1 as short as possible, because the osc-in pin becomes susceptible to external noise if the value of r 1 is large. = r 0 r 1 osc-out c 0 osc-out (msm5265) osc-in f osc f osc 1/2.2 c 0 r 0 r 1 3 10 r 0 v dd
msm5265 ? semiconductor 8/18 ? d/s when this pin is set at high level, the msm5265 operates in the 1/2 duty dynamic display mode, the msm5265 operates in the static display mode when this pin is set at low level. ? ext/int when the external common signal is used, fix this pin at high level and input the external common signal from the osc-in pin. the input common signal is used as the internal common signal and is output from the com-out pin through the buffer. when the built-in common signal generator is used, fix this pin at low level. when the msm5265 is used as an output expander, fix this pin at high level and the osc-in pin at low level. the output logic can be reveresed in respect to the input data by setting osc-in to "h" level. ? com-out when two or more msm5265s are connected in series (cascade connection), this pin should be connected with all of the slave msm5265's osc-in pins. ? sync this pin is an input/output pin which is used when two or more msm5265s are connected in series (cascade connection) in the 1/2 duty dynamic display mode. all of the involved msm5265's sync pins should be connected by the same line and they should be pulled up with a common resistor, which makes a phase level of all involved msm5265's com-a and com-b pins equal. when a single msm5265 is used in the dynamic display mode, sync should be pulled up with a resistor. connect this pin to gnd if any of the following conditions is true: C the msm5265 is operated in the static display mode C two or more msm5265 devices are cascade connected C a single msm5265 device is used C the msm5265 is used as an output expander ? data-in, clock the display data is serially input from the data-in pin to the 160-stage shift register at the rising edge of the clock pulse. the high level of the display data is used to turn the display on, while low level of the display data is used to turn off the display. ? data-out1 the 80th stage of the shift register contents is output from this pin. when two or more msm5265s are connected in series (cascade connection) in the static display mode, this pin should be connected to the next msm5265's data-in pin. ? data-out2 the 160th stage of the shift register contents is output from this pin. when two or more msm5265s are connected in series (cascade connection) in the 1/2 duty dynamic display mode, this pin should be connected to the next msm5265's data-in pin. ? load the signal for latching the shift register contents is input from this pin. when load pin is set at high level, the shift register contents are shifted to the 80 sets of lcd drivers. when this pin is set at low level, the last display data is held which was transfered to the 80 sets of lcd drivers when load pin was set at high level.
msm5265 ? semiconductor 9/18 ?v lc2 supply voltage pin for the 80 sets of lcd drivers. the input level to this pin should be the low level output voltage of segment outputs (seg 1 to seg 80 ) and common outputs (com-a, com-b). in this case, the high level of segment outputs and common outputs is the v dd level, while low level of segment outputs and common outputs is v lc2 level. v lc2 should be set at higher level than ground level. ?v lc1 supply voltage pin for the middle level voltage of the common outputs. the input level of this pin is the middle level output voltage of the common outputs (com-a, com-b) in the 1/2 duty dynamic display mode. the value of v lc1 is calculated by the following formula: v lc1 = (v dd + v lc2 )/2 in the static display mode, this pin should be open. ? com-a, com-b lcd driving common signals are output from these pins. these pins should be connected to the common side of the lcd panel. C in the static display mode a pulse in phase with the com-out output is output from both com-a and com-b. in this case, the high level is v dd, and the low level is v lc2 . C in the 1/2 duty dynamic display mode the com-a and com-b output signals are alternately changed within each com-out output cycle, resulting in alternate repetition of select and non-select modes. in the select mode, a signal in phase with the com-out signal is output at "h" (v dd ) and "l" (v lc2 ). in the non-select mode, a voltage is output at "m" (v lc1 ). in the select mode of com-a (non-select mode of com-b), signals that correspond to the 1st- to 80th-bit data of the data latch are output to the segment outputs. in the select mode of com-b (non-select mode of com-a), signals that correspond to the 81st- to 160th-bit data of the data latch are output to the segment outputs. com-out com-a com-b dynamic display mode (d/s : "h") static display mode (d/s : "l") v dd v lc1 v lc2 v dd v lc1 v lc2
msm5265 ? semiconductor 10/18 ? seg 1 to seg 80 lcd segment driving signals are output from these pins and they should be connected to the segment side of the lcd panel. "h" level : v dd , "l" level : v lc2 C in the static display mode the nth-bit data of the data latch (a) corresponds to the seg n. the data of the data latch (b) is invalid . a signal out of phase with the com-out signal is output to the segment outputs when the display is turned on, while a signal in phase with it is output when the display is turned off. C in the 1/2 duty dynamic display mode output of the seg n corresponds to as follows. when com-a is in select mode: nth-bit data of the data latch (a) when com-b is in select mode: nth-bit data of the data latch (b) when the display is turned on, a signal out of phase with the common signal corresponding to the data is output, while a signal in phase with the common signal is output when the display is turned off. com-a com-b dynamic display mode (d/s : "h") static display mode (d/s : "l") off off off off off on off on on off on off on on on on seg n com-a com-b seg n off on 80+n 80+n nn
msm5265 ? semiconductor 11/18 ? seg-test this pin is used to test the segment outputs (seg 1 to seg 80 ). all displays are turned on when this pin is set to high level. the display returns to the condition before the pin was set to high level. when this pin is at high level, the input on the blank pin is disabled. ? blank this pin is also used to test the segment outputs (seg 1 to seg 80 ). all displays are turned off when this pin is set to high level. the display returns to the condition before the pin was set to high level. when seg-test pin is at high level, the input on this pin is disabled.
msm5265 ? semiconductor 12/18 2) single msm5265 operation in the 1/2 duty dynamic display mode application circuits 1) single msm5265 operation in the static display mode r com 3 1.5 k w, r com 3 r lc from controller seg-test blank load data-in clock d/s ext/int osc-in osc-out sync v lc2 com-a seg 1 seg 80 r com x 2 lcd panel 80 x 2 segments (1/2 duty dynamic) v lc2 r 1 r 0 c 0 1 m w 100 k w 0.01 m f osc-out v lc1 com-b v dd r lc r lc v dd 22 k w com-a com-b msm5265 r com 3 1.5 k w from controller seg-test blank load data-in clock d/s ext/int osc-in osc-out sync v lc2 com-a seg 1 seg 80 com r com lcd panel 80 segments (static) r 1 r 0 c 0 1 m w 100 k w 0.01 m f osc-out msm5265 v dd
msm5265 ? semiconductor 13/18 80 80 80 r com r com r com lcd panel (80 x n segments) static com seg-test blank load data-in msm5265 com-a v lc2 com-out data-out 1 sync d/s ext/int osc data-in d/s ext/int sync data-out 1 com-a v lc2 osc-in d/s ext/int osc-in sync data-out 1 com-a v lc2 data-in msm5265 msm5265 v dd v dd r com 3 1.5 k w clock v lc2 3) cascade connections for msm5265s in the static display mode
msm5265 ? semiconductor 14/18 4) cascade connections for msm5265s in the 1/2 duty dynamic display mode 80 80 80 lcd panel (80 x n segments) 1/2 duty dynamic com-a seg-test blank load data-in msm5265 com-a com-out data-out 2 sync d/s ext/int osc data-in d/s ext/int sync data-out 2 com-a osc-in d/s ext/int osc-in sync data-out 2 com-a com-b data-in msm5265 msm5265 v dd v dd r com 3 1.5 k w, r com 3 r lc com-b r com r com r com clock r lc r lc v dd v lc2 com-b v dd 22k w v dd v lci v lc2 v lci v lc2 com-b v lci v lc2 r com r com r com
msm5265 ? semiconductor 15/18 from controller seg-test blank load data-in clock d/s ext/int osc-in sync v lc2 seg 1 seg 80 80 outputs (same logic as input data) v dd * * the output logic can be reversed with respect to the input data by setting osc-in to "h" level. msm5265 5) output-expander
msm5265 ? semiconductor 16/18 reference data i dd2 vs. v dd f com vs. r 0 , c 0 300 200 100 0 0 1 234567 v i dd2 m a v dd condition oscillating, no load room temperature r 0 =100k w c 0 =0.01 m f r 1 =1m w f osc vs. v dd v dd 1 234567 v hz 460 450 440 430 420 410 f osc +2% 0% C2% condition room temperature r 0 =100k w c 0 =0.01 m f r 1 =1m w c 0 =0.001 m f 56 68 82 100 120 150 180 220 r 0 k w f com hz 320 280 240 200 160 140 120 100 80 70 60 50 40 35 30 25 20 175 15 125 10 8.75 7.5 6.25 5 c 0 =0.0022 m f c 0 =0.0047 m f c 0 =0.01 m f c 0 =0.022 m f c 0 =0.047 m f condition d/s="l" ext/int="l" v dd =5.0v room temperature r 1 =10r 0 f com =1/8 f osc =1/ (17.6c 0 r 0 ) . .
msm5265 ? semiconductor 17/18 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfp100-p-1420-0.65-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.29 typ. mirror finish
msm5265 ? semiconductor 18/18 (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfp100-p-1420-0.65-bk package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.29 typ. mirror finish

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